Semiconductor apparatus having lateral type MIS transistor

ABSTRACT

A semiconductor apparatus comprises: a semiconductor substrate; and a lateral type MIS transistor disposed on a surface part of the semiconductor substrate. The lateral type MIS transistor includes: a line coupled with a gate of the lateral type MIS transistor; a polycrystalline silicon resistor that is provided in the line, and that has a conductivity type opposite to a drain of the lateral type MIS transistor; and an insulating layer through which a drain voltage of the lateral type MIS transistor is applied to the polycrystalline silicon resistor.

CROSS REFERENCE TO RELATED APPLICATION

The present application is based on Japanese Patent Application No.2007-73320 filed on Mar. 20, 2007, the disclosure of which isincorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to a semiconductor apparatus having alateral type MIS (Metal Insulator Semiconductor) transistor.

BACKGROUND OF THE INVENTION

Japanese Patent Application Publication 2001-352707 discloses asemiconductor apparatus in which an LDMOS (Lateral Diffused Metal OxideSemiconductor) transistor element is formed on a surface part of asemiconductor substrate.

A semiconductor apparatus 80 disclosed in JP-A-2001-352707 is describedbelow with reference to FIG. 11. The semiconductor apparatus 80 isformed with using a SOI (silicon on insulator) substrate that includes aP type silicon substrate 2, an insulating layer 3, an N type layer 1. Inthe semiconductor apparatus 80, an N type region 6 (i.e., a drift region6) is disposed so that the drift region 6 surrounds an N+ type drainregion 5. The N type region has higher concentration than the N typelayer 1. Concentration in the drift region 6 becomes higher as closer tothe N+ type drain region 5. A P+ type contact region 9 is adjacent toand adjoins an N+ type source region 8. The P+ type contact region 9extends so as to cover a part of the bottom side of the N+ type sourceregion 8. A LOCOS (Local Oxidation of Silicon) oxide layer 4 and a gateelectrode 11 are shown in FIG. 11.

The semiconductor apparatus 80 shown in FIG. 11 includes an LDMOStransistor element. A source and a drain of the LDMOS transistor elementare disposed in a surface layer of the N type layer 1. Carrier flowdirection is lateral. Since the LDMOS transistor element is capable ofbeing switched at higher speed compared to other switching elements, theLDMOS transistor element may be utilized in a switching circuit, aswitching power supply unit and the like, in which a switching elementis switched on and off at high speed.

Generally, such a switching circuit as a DC-DC converter and an inverteris operated at a higher operating frequency, and thus, requiredinductance and capacitance are small. In the above case, it may bepossible to configure a smaller switching circuit in accordance with therequired smaller inductance and capacitance. Therefore, a transistorhaving a high speed switching capability is desired, and the LDMOStransistor element may be suitable. However, in general, when atransistor (including the LDMOS transistor element) is switched at highspeed, a rapid voltage change causes a drain voltage overshoot (i.e.,surge voltage), and accordingly, strong noise (ringing) generation andswitching loss are caused.

Japanese Patent Application Publication 2004-6598, corresponding to U.S.Pat. No. 6,700,156, discloses a semiconductor apparatus associated witha transistor element used for a switching circuit.

A semiconductor apparatus 90 disclosed in JP-A-2004-6598 is describedbelow with reference to FIG. 12. The semiconductor apparatus 90 is asort of a VDMOS (Vertical Diffused Metal Oxide Semiconductor) transistorelement. A gate and a source of the device 90 are disposed in both sidesof a semiconductor substrate, respectively. The carrier flow directionis vertical. The semiconductor apparatus 90 shown in FIG. 12 ischaracterized by a P type layer 14. The P type layer 14 is adjacent to aP type base layer 12, and includes low-concentrated P-conductivity-typeimpurities. A conductivity type of the P type layer 14 is opposite tothat of a drain.

In the semiconductor apparatus 90 shown in FIG. 12, as a drain voltageis higher, a gate-to-drain capacitance increases due to existence of theP-type layer 14. As a result, a surge voltage generation in the drain issuppressed. The P-type layer effectively functions in the VDMOSstructured semiconductor apparatus 90. However, when a layer like theP-type layer 14 is disposed in a LDMOS structured semiconductor device,it is difficult to design a LDMOS semiconductor device due to its largeinfluence on a carrier channel. Moreover, in the semiconductor apparatus90, a flow of carriers through the low-impurity concentration P-typelayer 14 causes a larger on-state resistance. Furthermore, only theexistence of the P-type layer 14 may not sufficiently increase thegate-to-drain capacitance, and may not sufficiently suppress the surgevoltage generation.

SUMMARY OF THE INVENTION

In view of the above-described problem, it is an object of the presentdisclosure to provide a semiconductor apparatus having a lateral typeMIS transistor.

According to a first aspect of the present invention, a semiconductorapparatus comprises: a semiconductor substrate; a lateral type MIStransistor that is disposed on a surface part of the semiconductorsubstrate; a first line for a gate drive signal, the first line beingcoupled with a gate of the lateral type MIS transistor; apolycrystalline silicon resistor that is provided in the first line, andthat has a conductivity type opposite to a drain of the lateral type MIStransistor; and n insulating layer through which a drain voltage of thelateral type MIS transistor is applied to the polycrystalline siliconresistor.

According to the above semiconductor apparatus, when the drain voltageincreases, a depletion layer in the polycrystalline silicon resistor isenlarged. A drain voltage overshoot is reduced. Increase in noise andswitching loss is suppressed. Since the polycrystalline silicon resistoris made of polycrystalline silicon, a cost involved in thepolycrystalline silicon resistor is low. Since the polycrystallinesilicon resistor is capable of being formed in a variety of locations inthe semiconductor apparatus, it is possible to reduce dimensions of thesemiconductor apparatus.

According to a second aspect of the present invention, a semiconductorapparatus comprises: a semiconductor substrate that has a firstconductivity type; and a lateral type MIS transistor that is disposed ona surface part of the semiconductor substrate. The lateral type MIStransistor includes: an Insulating layer that is disposed on a surfaceof the semiconductor substrate; a drain region that has the firstconductivity type, and that is disposed on the Insulating layer so thatthe drain region is disposed in the semiconductor substrate; a driftregion that has the first conductivity type, and that is disposed in thesemiconductor substrate so that the drain region is disposed between thedrift region and the Insulating layer; a gate electrode that has thefirst conductivity type, and that is disposed on the insulating layer; apolycrystalline silicon resistor that has a second conductivity type,and that is disposed on the Insulating layer so that the Insulatinglayer is disposed between the polycrystalline silicon resistor and thedrift region; and a source region that has the first conductivity type,and that is disposed on the Insulating layer so that the source regionis disposed in the semiconductor substrate; a contact region that hasthe second conductivity type, and that is disposed on the insulatinglayer and adjacent to the source region. The semiconductor apparatusfurther comprises: a first line that is coupled with the gate electrode;and a second line that couples the polycrystalline silicon resistor withthe gate electrode. The first conductivity type is opposite to thesecond conductivity type. The polycrystalline silicon resistor has animpurity concentration approximately lower than 1×10¹⁷ cm⁻³. A drainvoltage of the lateral type MIS transistor is configured to be appliedto the polycrystalline silicon resistor through the insulating layer.

According to the above semiconductor apparatus, the semiconductorapparatus includes the lateral type MIS transistor. The source regionand the drain region are disposed on the surface part of thesemiconductor apparatus. Carries flow in the lateral direction. In theabove semiconductor apparatus, the polycrystalline silicon resistor isprovided in the first line. The drain voltage is applied to thepolycrystalline silicon resistor via the insulating layer. Thepolycrystalline silicon resistor has the impurity concentrationapproximately lower than 1×10¹⁷ cm⁻³, and therefore, the polycrystallinesilicon resistor functions as a MIS type transistor. Since aconductivity type of the polycrystalline silicon resistor is opposite tothat of the drain region, a depletion layer in the polycrystallinesilicon resistor expands when the drain voltage increases. Therefore, anovershoot of the drain voltage is reduced. In addition, noise generationand switching loss are suppressed.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the presentinvention will become more apparent from the following detaileddescription made with reference to the accompanying drawings. In thedrawings:

FIG. 1 is a schematic cross sectional view of a semiconductor apparatusaccording an example embodiment;

FIG. 2 is a circuit diagram of a switching circuit including anequivalent circuit of the semiconductor apparatus shown in FIG. 1, wherean area I surrounded by a dashed-dot line shown in FIG. 2 corresponds tothe semiconductor apparatus shown in FIG. 1;

FIG. 3A is a circuit diagram for describing parameters used for asimulation;

FIG. 3B is a graph showing a rate-of-rise characteristic of drainvoltage Vd as a function of time, the drain voltage Vd being obtainedfrom the simulation;

FIG. 4 is a schematic cross sectional view of a semiconductor apparatusaccording to a first modification embodiment;

FIG. 5A is a schematic cross sectional view of a semiconductor apparatusaccording to a second modification embodiment, the view being takenalong dashed-dot line VA-VA shown in FIG. 5B;

FIG. 5B is a schematic plan view illustrating a whole area of thesemiconductor apparatus according to the second modification embodiment;

FIG. 6A is a schematic cross sectional view of a semiconductor apparatusaccording to a third modification embodiment;

FIG. 6B is a schematic cross sectional view of a semiconductor apparatusaccording to a fourth modification embodiment;

FIG. 7A is a schematic cross sectional view of a semiconductor apparatusaccording to a fifth modification embodiment;

FIG. 7B is an enlarged view of an area surrounded by a dashed-dot lineVIIB described in FIG. 7A;

FIG. 7C is an enlarged view of an area VIIC surrounded by a dashed-twodot line described in FIG. 7A;

FIG. 8 is a schematic cross sectional view of a semiconductor apparatusaccording to a sixth modification embodiment;

FIG. 9 is a schematic cross sectional view of a seventh modificationsemiconductor apparatus;

FIG. 10 is a schematic cross sectional view of a semiconductor apparatusaccording to an eighth modification embodiment;

FIG. 11 is a schematic cross sectional view of a semiconductor apparatusaccording to the prior art;

FIG. 12 is a schematic cross sectional view of a semiconductor apparatusaccording to the prior art; and

FIG. 13 is a circuit diagram of a switching circuit including a drivecircuit utilizing a MOS transistor according to a related art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Japanese Patent Application No. 2006-204770 was filed, in which a drivecircuit for driving a MOS transistor is shown.

A switching circuit shown in the above application is described belowwith reference to FIG. 13. The switching circuit includes a drivecircuit for driving a MOS (metal-oxide-semiconductor) transistor as alateral type MIS transistor. In FIG. 13, an area surrounded by adash-line corresponds to a drive circuit K10 for driving a field-effecttransistor 20 (i.e., an N type MOS). The drive circuit K10 for drivingthe transistor 20 includes a MOS resistor 160. The MOS resistor 160provides a gate input resistance of the transistor 20.

In the switching circuit shown in FIG. 13, the transistor 20 isconnected between a load 30 and ground. A parasitic inductance isconnected between the transistor 20 and the load 30. The drive circuitK10 supplies a drive voltage Vin to a gate of the transistor 20, thedrive voltage Vin including a rectangular wave. The drive circuit K10switches on and off the transistor 20 based on the drive voltage Vin,and thereby, the drive circuit K10 switches on and off a DC (directcurrent) voltage Vdd supply from a power source 40 to the load 30.

The drive circuit K10 includes a drive voltage production circuit K11, afixed resistor R10, a first diode D10, a second diode D12, the MOSresistor 160. The fixed resistor R10 and the first diode D10 areconnected in series. The MOS resistor 160 and the second diode D12 areconnected in series. One pair including the fixed resistor R10 and thefirst diode D10 and the other pair including the MOS resistor 160 andthe second diode D12 are connected in parallel between the drive voltageproduction circuit K11 and the transistor 20. An anode of the firstdiode D10 is coupled with the drive voltage production circuit K11. Acathode of the first diode D10 is coupled with the transistor 20. Ananode of the second diode D12 is coupled with the transistor 20. Acathode of the second diode D12 is coupled with the drive voltageproduction circuit K11.

The MOS resistor 160 includes a first insulator region 162, a P typesemiconductor region 164 and a second insulator region 165. The firstinsulator region 162 and the second insulator region 165 are made of,for example, silicon oxide. The P type semiconductor region is made ofmonocrystalline silicon which includes P type impurities. The P typesemiconductor region 164 separates the first insulator region 162 fromthe second insulator region 165. A first electrode 161 faces the P typesemiconductor region 164 through the first insulator region 162. Asecond electrode 166 faces the P type semiconductor region 164 throughthe second insulator region 165. The first and second electrodes 161,166 are electrically connected with a drain electrode D of thetransistor 20. One end of the P type semiconductor region 164 iselectrically connected with a gate electrode G of the transistor via athird electrode 167. The other end of the P type semiconductor region164 is electrically connected with the drive voltage production circuitK11 via a fourth electrode 163. The MOS resistor 160 can control a widthof a depletion layer, which expands and contracts in a P typesemiconductor region by field-effect. A resistance R of the MOS resistor160 increases almost continuously in accordance with an applied voltageV. When a voltage Vds between the drain and the source is small, theresistance R of the MOS resistor 160 is adjusted to a small value. Whena voltage Vds between the drain and the source is large, the resistanceR is adjusted to a large value. The resistance R of the MOS resistor160, which corresponds to a gate input resistance, increases as thedrain voltage is higher. In the above manner, switching speeds are highin an initial stage of switching. In a late stage of switching where thevoltage overshoot poses a problem, the switching speed is caused to besmaller. The above configuration suppresses the generation of the surgevoltage in the drain in the late stage of switching.

Example Embodiment

A semiconductor apparatus 100 is described below with reference to FIGS.1-3. Note that, for the reason of simplification and easierunderstanding, a fixed resistor R10, a first diode D10 and a seconddiode D12, which are shown in FIG. 13, are omitted in FIG. 2.

As shown in FIG. 1, the semiconductor apparatus 100 includes asemiconductor substrate 10 and a lateral diffused metal oxidesemiconductor (LDMOS) transistor 21 as a lateral type MIS transistor.The LDMOS transistor 21 is disposed in a surface part of thesemiconductor substrate 10. As shown in FIGS. 1 and 2, a polycrystallinesilicon resistor 50 is provided in a line for a gate drive signal of theLDMOS transistor 21. The polycrystalline silicon resistor 50 is a P typeelement which is opposite to a drain (N type) of the LDMOS transistor21. The polycrystalline silicon resistor 50 is disposed on an insulatingfilm which includes a LOCOS (Local Oxidation of Silicon) oxide layer 4.The LOCOS oxide layer 4 is formed and disposed on a drift region 6 of adrain (D) of the LDMOS 21. In the above configuration, a drain voltageVd of the drift region 6 of the LDMOS 21 is applied to thepolycrystalline silicon resistor 50 via the LOCOS oxide layer 4.

The semiconductor apparatus 100 includes the LDMOS transistor 21. Asource (S) and the drain (D) are disposed in one surface part of thesemiconductor substrate 10. The LDMOS 21 having lateral carrier flowwith respect to the semiconductor substrate 10 can perform high-speedswitching compared to other transistor elements. The LDMOS 21 issuitably used for a switching circuit, a switching power supply and thelike.

Generally, as operating frequency of a switching circuit is changed to alarger value with using a high-speed transistor element such as theLDMOS 21, it is possible to reduce dimensions of the switching circuit.However, a voltage change at switching becomes large, and thus, theovershoot of the drain voltage becomes large (because of generation of asurge voltage and noise).

According to the semiconductor apparatus 100 shown in FIG. 1, thepolycrystalline silicon resistor 50 as a gate input resistor Rg isprovided in the line for the gate drive signal of the LDMOS transistor21. The polycrystalline silicon resistor 50 is a P type element which isopposite to a drain (N type) of the LDMOS transistor 21. The drainvoltage Vd is applied to the polycrystalline silicon resistor 50 via theinsulating film having the LOCOS oxide layer 4. A potential of thevoltage Vd is variable in switching. When an impurity concentration ofthe polycrystalline silicon resistor 50 is set to be lower than 1×10¹⁷cm⁻³ (i.e., p−), the polycrystalline silicon resistor 50 functions asthe MOS resistor shown in FIG. 13. Since the conductivity type of thepolycrystalline silicon resistor 50 is opposite to that of the drain,when the LDMOS 21 is switched to an off state and the drain voltage Vdis increased, a depletion layer is spread and a resistance is increased.Therefore, the LDMOS 21 switches at high speed in an initial stage ofthe switching since a resistance of the polycrystalline silicon resistor50 is small (i.e., a gate input resistance is small.). In a late stageof the switching, a switching speed of the LDMOS 21 decreases due to theincrease in the resistance of the polycrystalline silicon resistor 50.The polycrystalline silicon resistor 50 reduces overshoot of the drainvoltage Vd (i.e., surge voltage) and prevents the switching loss.

An effect of the polycrystalline silicon resistor 50 is evaluated bysimulation. Results of the simulation are shown in FIG. 3B. FIG. 3Ashows parameters on performing the simulation. FIG. 3B shows an initialrise characteristic of the drain voltage Vd in cases where the gateinput resistances Rg are set to be 3Ω and 30Ω, respectively.

As shown in FIG. 3B, when the gate input resistance Rg is changed from3Ω to 30Ω, a rate of rise of the drain voltage Vd is almost unchangedduring a period Ts, and an amplitude of the drain voltage Vd associatedwith the overshoot and ringing is reduced from Vr1 to Vr2.

The polycrystalline silicon resistor 50 of the semiconductor apparatus100 includes polycrystalline silicon and manufactured at a reasonablylow cost. The polycrystalline silicon resistor 50 is capable of beingformed at various region of the semiconductor substrate 10. Therefore,it is possible to reduce dimensions of the semiconductor apparatus 100shown in FIG. 1 compared the following two cases. One case is that theMOS resistor 160 (made from monocrystalline silicon) shown in FIG. 13 isdisposed in different location of a semiconductor substrate. The othercase is that the MOS resistor 160 is disposed separately from asemiconductor substrate. The drain voltage Vd of the drift region isapplied to the polycrystalline silicon resistor 50 via the LOCOS oxidelayer 4. The LOCOS oxide layer 4 is disposed on the drift region 6 ofthe drain of the LDMOS 21. The conductivity type of the polycrystallinesilicon resistor 50 is opposite to that of the drain. Since thepolycrystalline silicon resistor 50 may not cause a chip area of thesemiconductor apparatus 100 to increase, the semiconductor apparatus 100may have a simple structure, and accordingly, it is possible to reducedimensions of the semiconductor apparatus 100 and reduce a manufacturingcost.

The semiconductor apparatus 100 includes the LDMOS 21 capable ofswitching at high speed. In the semiconductor apparatus 100, thereducing of the overshoot of the drain voltage Vd suppresses the noiseand switching loss. The semiconductor apparatus 100 may be small and maybe manufactured at low cost.

A semiconductor apparatus 101 according to a first modificationembodiment is described below with reference to FIG. 4.

In the semiconductor apparatus 101, the polycrystalline silicon resistor50 is disposed on an insulating film 4A. The insulating film 4A isdisposed on the drift region 6 of the drain of the LDMOS 21. Aresistance of the polycrystalline silicon resistor 50 in thesemiconductor apparatus 101 depends on the drain voltage Vd moresensitive than that in the semiconductor apparatus 100. When the LDMOS21 is operated on low voltage, the above configuration may be effective.

A semiconductor apparatus 102 according to a second modificationembodiment is described below with reference to FIGS. 5A and 5B.

In the semiconductor apparatus 102, as shown in FIGS. 5A, 5B, thepolycrystalline silicon resistor 50 is disposed on a part of a surfaceof the LOCOS oxide layer 4. The part of the surface corresponds to aperiphery of an LDMOS 21A. The LDMOS 21A (i.e., a lateral type MIStransistor) is formed on the semiconductor substrate 10 (i.e., a chip).The drift region 6 of the drain is extended to an area corresponding tothe periphery of the LDMOS 21A.

When a LDMOS is used as a power element, the LDMOS may include multiplecells arranged in parallel. As shown in FIG. 5B, when a chip area hassufficient space, the polycrystalline silicon resistor 50 can bearranged on the periphery of a LDMOS 21A area. Therefore, a patterndesign can be simplified without changing a cell structure in the LDMOS21A formed area. In addition, it is possible to improve arrangementdegree of freedom for the polycrystalline silicon resistor 50.

In each semiconductor apparatus 100, 101, 102, the polycrystallinesilicon resistor 50 is disposed on the insulating film (i.e., the LOCOSoxide layer 4 or the insulating film 4A). The insulating film isdisposed on the drift region of the drain of the LDMOS 21, 21A. Thedrain voltage Vd is applied to the polycrystalline silicon resistor 50via the insulating film.

A semiconductor apparatus 103 according to a third modificationembodiment and semiconductor apparatus 104 according to a fourthmodification embodiment are described below with reference to FIG. 6Aand FIG. 6B, respectively.

Each semiconductor apparatus 103, 104 includes a wiring layer 16. Thewiring layer 16 is disposed over the polycrystalline silicon resistor 50through an interlayer insulating film 15. The wiring layer is coupledwith the drain of the LDMOS 21. In each semiconductor apparatus 103,104, the drain voltage Vd is applied to the polycrystalline siliconresistor 50 through the interlayer insulating film 15 and the wiringlayer 16. The conductivity type of the polycrystalline silicon resistor50 is opposite to that of the drain.

In the semiconductor apparatus 103 shown in FIG. 6A, the polycrystallinesilicon resistor 50 is disposed on the LOCOS oxide layer 4 which isformed on the drift region of the LDMOS 21. The drain voltage Vd isapplied to the polycrystalline silicon resistor 50 also through theLOCOS oxide layer 4 accordingly. In the semiconductor apparatus 103shown in FIG. 6A, the drain voltage Vd is applied from both sides of thepolycrystalline silicon resistor 50, and therefore, it is possible toprovide stronger drain voltage Vd dependence compared to thesemiconductor apparatus 100 shown in FIG. 1.

The semiconductor apparatus 104 shown in FIG. 6B is formed from asemiconductor substrate having an SOI (Silicon on Insulator) structure.The semiconductor apparatus 104 includes a P type silicon substrate 2,an insulating layer 3, and an N type layer 1. An electrical separationtrench electrically separates the LDMOS 21 from surrounding elements.The electrical separation trench includes a side-wall insulating layer17 and a polycrystalline silicon 18. The polycrystalline silicon 18 isembedded in the electrical separation trench through the side-wallinsulating layer 17. The polycrystalline silicon resistor 50 of thesemiconductor apparatus 104 is disposed on a part of the LOCOS oxidelayer 4, the part being disposed outside of the electrical separationtrench. The drain voltage Vd is applied almost only through the wiringlayer 16. The wiring layer 16 connects the interlayer insulating film 15and the drain of the LDMOS 21.

The semiconductor apparatuses 103, 104 shown in FIGS. 6A, 6B have simplestructure, and are capable of being manufactured at low cost.

A semiconductor apparatus 105 according to a fifth modificationembodiment is described below with reference to FIGS. 7A, 7B, 7C.

In the semiconductor apparatus 105 shown in FIGS. 7A, 7B, 7C, thepolycrystalline silicon 18 has low concentration (with respect to p−)and is embedded in the electrical separation trench through theside-wall insulating layer 17. The polycrystalline silicon 18 of thesemiconductor apparatus 105 provides a polycrystalline silicon resistor51. The polycrystalline silicon resistor 51 functions as thepolycrystalline silicon resistor 50 of the semiconductor apparatuses100-104 shown in FIGS. 1-6. In the semiconductor apparatus 105, thepolycrystalline silicon 18 is provided in the line for the gate drivesignal of the LDMOS transistor 21. The conductivity type of thepolycrystalline silicon resistor 51 is opposite to that of the drain ofthe LDMOS transistor 21. The drain voltage Vd of the drift region 6 ofthe LDMOS transistor 21 is applied to the polycrystalline siliconresistor 51 of the polycrystalline silicon 18 through the side-wallinsulating layer 17. In the semiconductor apparatus 105, the overshootof the drain voltage Vd (i.e., surge voltage) is reduced, and the noiseand the switching loss are suppressed.

Since the polycrystalline silicon resistor 51 is disposed in the trench,the increase in a chip area associated with the existence of thepolycrystalline silicon resistor 51 is also suppressed.

In each semiconductor apparatus 100-105 shown in FIGS. 1-7, thepolycrystalline silicon resistor 50, 51 is connected with the gateelectrode 11 by a line. The gate electrode 11 is provided by a part ofpolycrystalline silicon in the LDMOS 21. Alternatively, thepolycrystalline silicon resistor 50, 51 and the gate electrode 11 of theLDMOS 21 may integrally formed since the polycrystalline siliconresistor 50, 51 and the gate electrode 11 of the LDMOS 21 are providedby a same polycrystalline silicon.

Semiconductor apparatuses 106-108 are described below. In eachsemiconductor apparatus 106-108, the polycrystalline silicon resistorand the gate electrode of the LDMOS are combined.

The semiconductor apparatus 106 according to a sixth modificationembodiment is described below with reference to FIG. 8. The conductivitytype of a polycrystalline silicon resistor 52 is different from that ofthe gate electrode 11 in order to control a threshold voltage of theLDMOS 21. Ion-implantation forms regions in the integrally formed gateelectrode and the polycrystalline silicon resistor. The ion-implantedregions formed in the gate electrode and the polycrystalline siliconresistor may have different conductivity type and different impurityconcentration from each other, resulting from different impuritiesimplantation. When, similar to the semiconductor apparatus 106, theconductivity type of the gate electrode is different from that of thepolycrystalline silicon resistor, it may be preferable that a part ofthe polycrystalline silicon resistor is configured to touch the gateelectrode 11 and a silicide layer 11A or a metal layer is formed. In theabove manner, the silicide layer 11A shorts the part of thepolycrystalline silicon resistor and the gate electrode. The gateelectrode 11 is connected with the polycrystalline silicon resistor in asimple configuration even if the conductivity types are different fromeach other.

In the semiconductor apparatus 107 shown in FIG. 9 according to aseventh modification embodiment, the polycrystalline silicon resistorand a gate electrode of an LDMOS 22 (i.e., a lateral type MIStransistor) have the same conductivity type (i.e., P type). In the abovecase, although a threshold voltage of the LDMOS 22 increases, since aparticular structure to connect between the polycrystalline siliconresistor and the gate electrode is not required, the semiconductorapparatus 107 has a simplified structure and a low manufacturing cost.

The semiconductor apparatus 108 according to an eighth modificationembodiment is described below with reference to FIG. 10. A gateelectrode 11 of an LDMOS 23 (i.e., a lateral type MIS transistor) and apolycrystalline silicon resistor 54 are integrally formed from a same Nconductivity type polycrystalline silicon. A conductivity type of thesemiconductor apparatus 108 shown in FIG. 10 is opposite to that of thesemiconductor apparatus 107 shown in FIG. 9. While the semiconductorapparatus 107 shown in FIG. 9 includes an n-channel LDMOS 23, thesemiconductor apparatus 108 shown in FIG. 10 includes a p-channel LDMOS23. In the semiconductor apparatus 108 shown in FIG. 10, thepolycrystalline silicon resistor 54 is disposed on the LOCOS oxide layer4. The LOCOS oxide layer 4 is disposed in and formed in a drift region6A that has a P type conductivity. The drain voltage Vd of the driftregion 6A of the LDMOS 23 is applied to the polycrystalline siliconresistor 54. In the semiconductor apparatus 108, since the conductivitytype of the polycrystalline silicon resistor 54 is opposite to that ofthe drain D, the overshoot of the drain voltage Vd (i.e., surge voltage)is reduced. Furthermore, Suppressing noise (i.e., linking) andpreventing the increase in the switching loss are achieved.

In each semiconductor apparatus 106-108, a line for connecting betweenthe gate electrode 11, 13 and the polycrystalline silicon resistor 51,53, 54 is no required. Lowering wiring efficiency due to arrangement ofthe polycrystalline silicon resistor 51, 53, 54 is suppressed.

Each semiconductor apparatus shown in FIGS. 1-10 includes the LDMOStransistor having a high-speed switching capability, is capable of beingconfigured to be small size, and is capable of being manufactured at lowcost. Furthermore, the overshoot of the drain voltage is reduced, andthe increase in the switching loss is suppressed.

While the invention has been described with reference to preferredembodiments thereof, it is to be understood that the above-describedembodiments and constructions. In addition, while the variouscombinations and configurations, which are preferred, other combinationsand configurations, including more, less or only a single element, arealso within the spirit and scope of the invention.

1. A semiconductor apparatus comprising: a semiconductor substrate; alateral type MIS transistor that is disposed on a surface part of thesemiconductor substrate; a first line for a gate drive signal, the firstline being coupled with a gate of the lateral type MIS transistor; apolycrystalline silicon resistor that is provided in the first line, andthat has a conductivity type opposite to a drain of the lateral type MIStransistor; and an insulating layer through which a drain voltage of thelateral type MIS transistor is applied to the polycrystalline siliconresistor.
 2. The semiconductor apparatus according to claim 1, whereinthe lateral type MIS transistor further includes a drift region disposedin the drain, the insulating layer is disposed on the drift region, andthe polycrystalline silicon resistor is disposed on the insulatinglayer.
 3. The semiconductor apparatus according to claim 2, wherein theinsulating layer includes a LOCOS oxide layer.
 4. The semiconductorapparatus according to claim 3, wherein the polycrystalline siliconresistor is disposed on a periphery of the lateral type MIS transistor.5. The semiconductor apparatus according to claim 1, wherein theinsulating layer provides an interlayer insulating film, and theinterlayer insulating film is disposed over the semiconductor substrate.6. The semiconductor apparatus according to claim 1, wherein the lateraltype MIS transistor further includes a drift region and a trench,wherein the drift region is disposed in the drain, the trench isdisposed in the drift region, the insulating layer is a side-wallinsulating layer of the trench, and the polycrystalline silicon resistoris disposed on the side-wall insulating layer and disposed in thetrench.
 7. The semiconductor apparatus according to claim 1, wherein thelateral type MIS transistor further includes a gate electrode that isconnected with the polycrystalline silicon resistor via a second line.8. The semiconductor apparatus according to claim 1, wherein the lateraltype MIS transistor further includes a gate electrode made ofpolycrystalline silicon, and the gate electrode and the polycrystallinesilicon resistor are integrated in the lateral type MIS transistor. 9.The semiconductor apparatus according to claim 8, further comprising: asilicide layer 11A disposed between the gate electrode and thepolycrystalline silicon resistor, and a conductivity type of thepolycrystalline silicon resistor is different from a conductivity typeof the gate electrode.
 10. The semiconductor apparatus according toclaim 8, wherein the polycrystalline silicon resistor and the gateelectrode have a same conductivity type.
 11. The semiconductor apparatusaccording to claim 8, further comprising: a metal layer disposed betweenthe gate electrode and the polycrystalline silicon resistor, and aconductivity type of the polycrystalline silicon resistor is differentfrom a conductivity type of the gate electrode.
 12. The semiconductorapparatus according to claim 1, wherein the polycrystalline siliconresistor has an impurity concentration approximately lower than 1×10¹⁷cm⁻³.
 13. A semiconductor apparatus comprising: a semiconductorsubstrate that has a first conductivity type; a lateral type MIStransistor that is disposed on a surface part of the semiconductorsubstrate, the lateral type MIS transistor including: an Insulatinglayer that is disposed on a surface of the semiconductor substrate; adrain region that has the first conductivity type, and that is disposedon the Insulating layer so that the drain region is disposed in thesemiconductor substrate; a drift region that has the first conductivitytype, and that is disposed in the semiconductor substrate so that thedrain region is disposed between the drift region and the Insulatinglayer; a gate electrode that has the first conductivity type, and thatis disposed on the insulating layer; a polycrystalline silicon resistorthat has a second conductivity type, and that is disposed on theInsulating layer so that the Insulating layer is disposed between thepolycrystalline silicon resistor and the drift region; a source regionthat has the first conductivity type, and that is disposed on theInsulating layer so that the source region is disposed in thesemiconductor substrate; and a contact region that has the secondconductivity type, and that is disposed on the insulating layer andadjacent to the source region; a first line that is coupled with thegate electrode; and a second line that couples the polycrystallinesilicon resistor with the gate electrode, wherein the first conductivitytype is opposite to the second conductivity type, the polycrystallinesilicon resistor has an impurity concentration approximately lower than1×10¹⁷ cm⁻³, and a drain voltage of the lateral type MIS transistor isconfigured to be applied to the polycrystalline silicon resistor throughthe insulating layer.